The present invention relates to a device and method for arithmetic processing that executes instructions according to, for example, a microprogram and then selectively performs a predetermined arithmetic and logic operation such as rounding or saturation, to instruction-execution results.
Conventionally, there are arithmetic processing devices for the purpose of numerical arithmetic operations. The arithmetic processing device is configured of a numerical arithmetic section for executing a numerical arithmetic operation according to a statement described with a program and a register group for temporarily storing an input value to the numerical arithmetic section or the arithmetic result. Numerical values are exchanged via the register group.
In that type of arithmetic processing devices, a long data length is set in the numerical arithmetic section to improve the arithmetic accuracy. For that reason, when the numerical arithmetic section stores an arithmetic result to the memory or outputs it to external circuits, a predetermined process is carried out to shorten the data length. The so-called rounding process of rounding the lower bits of an arithmetic result or the so-called saturation process of saturating to a value by discarding the upper bits when an arithmetic result exceeds a predetermined value is well known as the predetermined process.
For that reason, the above arithmetic processing device generally contains a processing section and the so-called mode register. The processing section performs a predetermined process such as rounding or saturation, when the register group stores an arithmetic result from the numerical arithmetic section. The so-called mode register sets a flag which designates whether or not a predetermined process such as rounding is performed to the arithmetic result of the numerical arithmetic section.
Whether or not the above special process is needed to carry out to an arithmetic result of the numerical arithmetic section is defined by a program describing a series of process procedures. If necessary, xe2x80x9c1xe2x80x9d, for example, is written as a flag for the mode register. The flag to the mode register is rewritten every time the special process is performed.
In a program, for example, for a microprocessor, an instruction of executing a saturation process to an arithmetic execution result and an instruction of executing no saturation process may be alternately performed. In such a case, it is required to add the statement that resets a flag of the mode register for each instruction in each process on a program. The problem is that adding a statement leads to increasing the code size of the program and the number of execution steps so that the volume of the program is expanded.
The objective of the present invention is to solve the above-described tasks.
Furthermore, the objective of the invention is to provide an arithmetic processing device and method that can suppress an increase of the volume of a program describing a series of numerical arithmetic execution procedures even when a predetermined process is intermittently repeated to an instruction execution result.
In order to overcome the above mentioned problems, an arithmetic processing device of the present invention comprises a first register group (for example, a constituent element corresponding to the register group 40, to be described later) for storing an instruction execution result (for example, a factor corresponding to the arithmetic result A of the numerical arithmetic circuit 50, to be described later) executed according to a program which describes a series of procedures. A predetermined arithmetic and logic operation (for example, a constituent element corresponding to a specific process of the specific processing circuit 60, to be described later) is selectively performed to said instruction execution result when the first register group stores the instruction execution result. The arithmetic processing device further has a second register (for example, a constituent element corresponding to the mode register 20, to be described later) arranged corresponding to the first register group, for setting a flag specifying whether or not the arithmetic and logic operation is performed to an instruction execution result to be stored in a register including in the first register group specified on the program.
In the configuration of the arithmetic processing device, a flag designating whether to perform a predetermined arithmetic and logic operation to an instruction execution result is set to the second register. The bit of the second register corresponds to the first register. When a register in the first register group, to which an instruction execution result is stored, is designated on a program, whether to perform a predetermined process to the instruction execution result is determined according to the flag set to a bit of the second register corresponding to the designated register. In other words, if a flag is previously set to the second register, the presence or absence of a predetermined arithmetic and logic operation is determined by selecting a register, that is, a destination storing the instruction execution result. Therefore, it is unnecessary to vary a flag to designate whether to perform a predetermined arithmetic and logic operation on the program every operation. As a result, the statement on the program for setting a flag can be reduced.
Moreover, according to the present invention, an arithmetic processing device, wherein an instruction is executed according to a program which describes a series of procedures and a predetermined arithmetic and logic operation (for example, a constituent element corresponding to a specific process of the specific processing circuit 60, to be described later) is selectively performed to the instruction execution result (for example, a factor corresponding to an arithmetic result A of the numerical arithmetic circuit 50, to be described later), comprises a program storage section (for example, a constituent element corresponding to the program memory 10, to be described later) for storing said program; an instruction execution section (for example, a constituent element corresponding to the numerical arithmetic circuit 50, to be described later) for executing an instruction described in said program; a first register group (for example, a constituent element corresponding to the register group 40, to be described later) for storing an instruction execution result from said instruction execution section; an arithmetic processing section (for example, a constituent element corresponding to the specific processing circuit 60, to be described later) for performing a predetermined arithmetic and logic operation of said instruction execution result; a second register (for example, a constituent element corresponding to the mode register 20, to be described later) arranged corresponding to said first register, for designating whether or not said predetermined arithmetic and logic operation is performed, to said instruction execution result of said instruction execution result; and a control section (for example, a constituent element corresponding to the decoder 30, to be described later) for controlling said arithmetic and logic operation to said instruction execution result, by referring to a flag (for example, a constituent element corresponding to the flag set to the bits MR0 to MR7 of the mode register 20, to be described later) set to said second register corresponding to registers (for example, a constituent element corresponding to the registers MR0 to MR7, to be described later) forming said first register group designated on said program when said instruction execution result is stored in said first register group, said register acting as a register storing said instruction execution result.
According to the above configuration of the arithmetic processing device, when an instruction execution result is stored into the first register group, the control section controls a predetermined arithmetic and logic operation of the instruction execution result. When a register in the first register group, to which the instruction execution result is stored, is designated on the program, the control section refers to a flag set to the bit of the second register, being a bit corresponding to the designated register. Thus, the control section controls a predetermined process to the instruction execution result according to the flag. In other words, when a flag is previously stored in the second register, whether to perform a predetermined logic operation is controlled by selecting a register being a destination to which the instruction execution result is stored. Therefore, it is unnecessary that a flag to designate whether to perform a predetermined arithmetic and logic operation is varied on the program every operation cycle. As a result, the statement described on the program for setting a flag can be reduced.
The control section, for example, controls the arithmetic processing section to selectively execute the predetermined arithmetic and logic operation of the instruction execution result of the instruction execution section, according to the flag.
In the above configuration of the arithmetic processing device, since a predetermined arithmetic and logic operation is controlled according to a flag, the frequency of the operation of the arithmetic processing section can be suppressed at minimum.
The control section, for example, controls the arithmetic processing unit to uniformly execute the arithmetic and logic operation of an instruction execution result of the instruction execution section, selecting an instruction execution result (for example, a constituent element corresponding to the arithmetic result A of the numerical arithmetic circuit 50) of the instruction execution section or an arithmetic result of the arithmetic processing section (for example, a constituent element corresponding to the arithmetic result B of the specific processing circuit 60) according to the flag, and thus storing the selected result into the first register group.
In the above configuration of the arithmetic processing device, the arithmetic processing section uniformly performs independently of the content of a flag so that the result of instruction execution or predetermined arithmetic and logic operation is selected according to the flag. Hence, a flag can be referred to during a predetermined process so that the logic operation can be performed at high speed.
The second register, for example, has a plurality of bits corresponding to the first register group and a control bit (for example, a factor corresponding to the bit RENA) for setting a control flag determining whether or not flags set by the plurality of bits are validated.
In the above configuration of the arithmetic processing device, whether to perform a predetermined arithmetic and logic operation to an instruction execution result can be controlled according the flag set to the second register by rewriting the control flag only, without rewriting bits corresponding to the first register group, or the bit of the second register. Thus, errors that may occur in rewriting a flag can be prevented previously. Whether to perform a arithmetic and logic operation can be certainly controlled according to the flag set to the second register.
The second register, for example, has a plurality of bits corresponding to the first register group and a plurality of second control bits (for example, factors corresponding to the registers RENA1 and RENA2) for setting plural control flags corresponding to the content of the predetermined arithmetic and logic operation, the plural control bits determining whether or not flags set by the plurality of bits are validated.
In the above configuration of the arithmetic processing device, the control flag is selectively rewritten according to the content of a predetermined arithmetic and logic operation of the arithmetic processing section. Thus, whether the arithmetic processing section performs an arithmetic and logic operation to an instruction execution result of the instruction execution section can be controlled for each content of the arithmetic and logic operation, without rewriting bits corresponding to the first register or the bit of the second register. Accordingly, another process such as rounding can be controlled to the instruction execution result, in addition to the special process such as saturation process.
Moreover, according to the present invention, an arithmetic processing method, wherein an instruction is executed according to a program on which a series of procedures are described and a predetermined arithmetic and logic operation is selectively performed to the instruction execution result (for example, a factor corresponding to an arithmetic result of the numerical arithmetic circuit 50), thus storing the arithmetic result into the first register group, comprises (a) a first step (for example, a factor corresponding to the step S10) of setting a flag to a second register corresponding to a register included in the plural first register group designated on the program, the register acting as a register storing the instruction execution result; (b) a second step (for example, a factor corresponding to the step S11) of executing an instruction described on the program; (c) a third step (for example, a factor corresponding to the steps S12 to S13) of controlling the predetermined arithmetic and logic operation to the instruction execution result, by referring to a flag set to the second register when the first register group stores the instruction execution result; and (d) a fourth step (for example, a factor corresponding to the step 14) of storing an instruction execution result subjected to the predetermined arithmetic and logic operation into the first register group.
According to the above method, a flag designating whether to perform a predetermined arithmetic and logic operation to an instruction execution result is set to the second register. The bit of the second register corresponds to the first register group. When one of registers in the first register group, to which an instruction execution result is stored, is designated on a program, whether to perform a predetermined process to the instruction execution result is determined according to the flag set to the bit of the second register corresponding to the designated register. In other words, if a flag is previously set to the second register, the presence or absence of a predetermined arithmetic and logic operation is determined by selecting a register, that is, a destination storing the instruction execution result. Therefore, it is unnecessary that a flag for designating whether to perform a predetermined arithmetic and logic operation is varied on the program for each operation. As a result, the statement on the program for setting a flag can be reduced.
In the third step, the predetermined arithmetic and logic operation of the instruction execution result of the instruction execution result is selectively executed according to the flag.
In the above method, since a predetermined arithmetic and logic operation, for example, is controllably executed according to a flag, the execution frequency of the predetermined arithmetic processing can be suppressed at minimum.
In the third step, the selected result is stored into the first register group by uniformly executing the arithmetic and logic operation of an instruction execution result and by selecting the instruction execution result or an arithmetic result of the predetermined arithmetic processing, according to a flag set to the second register (for example, a factor corresponding to steps S22 to S25).
According to the above method, a predetermined arithmetic and logic operation is uniformly performed independently of the content of a,flag to select an instruction execution result or a predetermined arithmetic and logic operation according to the flag. Hence, a flag can be referred to during the predetermined process so that the logic operation can be performed at high speed.
In the first step, a flag is set to said second register bit being a bit corresponding to the first register group and a control bit is set to the control bit of the second register. The control bit determines whether or not the flag is validated. In the third step, a control bit set to the control bit of the second register is referred to in advance of a flag set to the bit of the second register, the bit of the second register being a bit corresponding to the first register group. The flag corresponding to said first register group is referred to when the content of the control flag is affirmative, so that the predetermined arithmetic and logic operation is controlled.
According to the above method, whether to validate the flag set to the bit of the second register group being the bit corresponding to the first register group is determined by the control flag. In other words, only when validating a flag to which the control flag is set to the second register is affirmative, a predetermined arithmetic and logic operation is performed to an instruction execution result by referring to the flag set to the second register corresponding to the first register group. When validating the flag to which the control flag is set to the second register is negative, the flag set to the second register corresponding to the first register group is ignored. Thus, the predetermined arithmetic and logic operation is not executed at all. Whether to perform a predetermined arithmetic and logic operation to an instruction execution result can be controlled without rewriting the flag set to the bit of the second register being the bit corresponding to the first register.